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ISDB-T Single-Segment Low-IF Tuners
Pin Description (continued)
PIN
TQFN
BUMP NO.
WLP
NAME
DESCRIPTION
DC Power Supply for Baseband Filter Circuits. Connect to a +2.85V low-noise
20
39
VCCFLT
supply. Bypass to GND with a 100pF capacitor connected as close to the pin as
possible. Do not share capacitor ground vias with other ground connections.
XTAL/TCXO Select. Logic-high enables the TCXO input and disables the XTAL input.
22
37
ENTCXO
Logic-low disables the TCXO input and enables the XTAL input. This pin is internally
pulled up to V CC .
23
25
26
27
47
44
—
43
GC2
IOUT
GNDBB
QOUT
Baseband Gain-Control Input. High-impedance analog input, with a 0.3V to 2.7V
operating range. V GC2 = 0.3V corresponds to the maximum gain setting.
In-Phase Low-IF Output. Requires a DC-blocking capacitor.
Ground for Baseband Circuits. Connect to the PC board ground plane.
Quadrature Low-IF Output. Requires a DC-blocking capacitor.
DC Power Supply for Baseband Circuits. Connect to a +2.85V low-noise supply.
29
41
VCCBB
Bypass to GND with a 100pF capacitor connected as close to the pin as possible.
Do not share capacitor ground vias with other ground connections.
Internal VCO Bias Bypass. Bypass directly to GNDVCO with a 470nF capacitor
32
30
VCOBYP
connected as close to the pin as possible. Do not share capacitor ground vias with
other ground connections. See the Layout Considerations section.
DC Power Supply for VCO Circuits. Connect to a +2.85V low-noise supply. Bypass
33
26
VCCVCO
directly to GNDVCO with a 100pF capacitor connected as close to the pin as
possible. Do not share capacitor ground vias with other ground connections.
34
35
36
37
38
23
32
20
18
16
GNDVCO
VTUNE
GNDTUNE
TEST
CPOUT
VCO Circuit Ground. Connect to the PC board ground plane. See the Layout
Considerations section.
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this
pin with the shortest connection as possible.
Ground for VTUNE. Connect to the PC board ground plane. See the Layout
Considerations section.
Test Output. Used as a test output for various internal blocks. See Table 2.
Charge-Pump Output. Connect this output to the PLL loop filter input with the
shortest connection possible.
DC Power Supply for Charge-Pump Circuits. Connect to a +2.85V low-noise supply.
39
10
VCCCP
Bypass to GND with a 100pF capacitor connected as close to the pin as possible.
Do not share capacitor ground vias with other ground connections.
40
EP
—
—
1
—
3, 6, 8, 13, 15,
27, 31, 40, 42
21
GNDCP
GND
GND
GNDLNA
Charge-Pump Circuit Ground. Connect to the PC board ground plane. See the
Layout Considerations section.
Exposed Paddle (TQFN Only). Solder evenly to the board’s ground plane for proper
operation.
Ground. Connect to the PC board ground plane.
Ground for LNA. Connect to ground with trace.
10
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